Herzel, F. Huang, Q.
Phase locked loop working
Je-Kwang, C. Kampe, A. Lee, T. Leeson, D.
IEEE L. Leung, G. Levantino, S. Manetakis, K. Soares, N. Pellerano, S. Perrott, M.
Quemada, C. Rategh, H.
Razavi, B. Rohde, U. Sjoland, H. Svelto, F. Valla, M. Vassiliou, I. Wang: A 1.
Wohlmuth, H. In: Proc.
Design methodology for RF CMOS phase locked loops - CERN Document Server
Solid State Circuits Conf. Yu, D. Yuan, J. Zargari, M.
He received his M. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors.
The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect.
You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications.
Determination of Building Blocks Specifications. PLL Fundamentals.